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RM0008
18.6
18.6.1
Window watchdog (WWDG)
WWDG registers
Refer to Section 1.1 on page 37 for a list of abbreviations used in register descriptions.
Control register (WWDG_CR)
Address offset: 0x00
Reset value: 0x7F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDGA
T6
T5
T4
T3
T2
T1
T0
Reserved
rs
rw
rw
rw
rw
rw
rw
rw
Bits 31:8 Reserved
Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every (4096 x
2 WDGTB ) PCLK1 cycles. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes
cleared).
18.6.2
Configuration register (WWDG_CFR)
Address offset: 0x04
Reset value: 0x7F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
EWI
rs
WDG
TB1
rw
WDG
TB0
rw
W6
rw
W5
rw
W4
rw
W3
rw
W2
rw
W1
rw
W0
rw
Bit 31:10 Reserved
Bit 9 EWI: Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is
only cleared by hardware after a reset.
Doc ID 13902 Rev 9
407/995
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